Non-volatile two-transistor semiconductor memory cell and method for producing the same

ABSTRACT

The invention relates to a nonvolatile semiconductor memory cell and to an associated fabrication method, a source region ( 7 ), a drain region ( 8 ) and a channel region lying in between being formed in a substrate ( 1 ). In order to realize locally delimited memory locations (LB, RB), an electrically non-conductive charge storage layer ( 3 ) situated on a first insulation layer ( 2 ) is divided by an interruption (U), thereby preventing, in particular, a lateral charge transport between the memory locations (LB, RB) and significantly improving the charge retention properties.

PRIORITY AND CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to and claims the benefit of priority under35 U.S.C. §§ 120 and 365 of international patent application numberPCT/DE02/04522, filed on Dec. 10, 2002, which was published asinternational publication number WO03/061014 A1, in German.

This application is further related to and claims the benefit ofpriority under 35 U.S.C. §§ 119 to the filing date of Jan. 15, 2002 ofGerman patent application number 10201304.7, filed on Jan. 15, 2002.

The present invention relates to a nonvolatile semiconductor memory celland to an associated fabrication method and, in particular, to aso-called dual bit EEPROM memory cell.

As an alternative to conventional mechanical storage devices, recentlynonvolatile semiconductor memory devices having nonvolatilesemiconductor memory cells such as, for example, FLASH, EPROM, EEPROM,FPGA memory cells and the like have gained greater and greateracceptance. Such rewritable nonvolatile semiconductor memory cells canstore data over a long period of time and without the use of a voltagesupply.

Such semiconductor memory cells usually comprise a semiconductorsubstrate, an insulating tunnel layer, a storage layer, an insulatingdielectric layer and a conductive control layer. In order to storeinformation, charges are introduced into the charge-storing layer from asemiconductor substrate. Examples of methods for introducing the chargesinto the storage layer are injection of hot charge carriers andFowler-Nordheim tunnelling.

In particular, an information content per unit area, the chargeretention properties and the operating voltages for reading andprogramming are of importance in the realization of such nonvoltatilesemiconductor memory cells. In order to improve a charge retention time,in this case use has increasingly been made in particular of nonvolatilesemiconductor memory cells with electrically non-conductive chargestorage layers, as a result of which, even in the case of partlyinadequate insulation layers, a leakage current can be prevented and thecharge retention properties can thus be improved.

Furthermore, so-called multibit semiconductor memory cells have beendeveloped, which can realize a multiplicity of information contents orbits in a memory cell. The information content per unit area has beenable to be significantly improved in this way.

The present invention relates, in particular, to a dual bitsemiconductor memory cell with which two bits can be stored innonvolatile fashion.

Such a dual bit semiconductor memory cell is known for example from thedocument U.S. Pat. No. 6,011,725 and is described below by means of FIG.1.

In accordance with FIG. 1, such a two-bit EEPROM memory cell has asemiconductor substrate 1, which is p-doped, for example, and which hasan n⁺-doped source region 7 and drain region 8 with associated terminalssource and drain terminals S and D. It should be pointed out that asymmetrical construction is used in such a cell, for which reason theterms source and drain are not necessarily meaningful. In actual fact,the source region 7, for example, can also be connected as the drainregion and the drain region 8 can also be connected as the sourceregion.

In accordance with FIG. 1, the source and drain regions 7 and 8 define achannel region lying in between. A first insulation layer 2, anelectrically non-conductive charge storage layer 3, a second insulationlayer 4 and an electrically conductive control layer 10, which has agate terminal G, are situated at the surface of said channel region. Inaccordance with FIG. 1, silicon nitride is used as the electricallynon-conductive charge storage layer 3. For the programming, i.e. writingand erasing of this conventional nonvolatile semiconductor memory cell,an injection of hot charge carriers is essentially carried out, in whichcase, for writing, for example hot electrons are injected into thecharge storage layer 3 on the drain side and, for erasing, hot holes areinjected on the drain side. Since a symmetrical dual bit memory cell isinvolved, it is also possible, in the same way, for charge carriers tobe injected into the charge storage layer 3 on the source side, in whichcase, however, the source region 7 is connected as the drain. Withregard to the method for reading from, writing to and erasing such amemory cell, reference is explicitly made to the document U.S. Pat. No.6,011,725.

Although extraordinarily high charge retention properties are alreadyobtained at relatively low programming voltages in the case of such aconventional semiconductor memory cell, disadvantages have nonethelessbeen found which are of importance in particular in the case of amultiple programming over a long period of time. This is due inparticular to the fact that the hot holes required for erasing aregenerally generated by means of an avalanche effect in the field of thep-n diode and therefore do not fall exactly at the same place in thecharge storage layer 3 as the hot electrons introduced in the course ofwriting. For a memory location RB (right bit) arranged on the right, inthe same way as for a left memory location LB (left bit) arranged on thesource side, the problem arises that the electrons and holes are notintroduced exactly at the same place and, consequently, a slight chargeshift takes place. This imprecise compensation generally leads tothreshold value shifts in the memory cell and thus to read currentchanges. This in turn causes an increased inaccuracy in an evaluationcircuit (not illustrated).

A further point whereby the charge retention properties of thisconventional semiconductor memory cell are adversely affected is causedby the fact that even though the charge storage layer 3 is electricallynon-conductive, a small charge movement nevertheless takes place. Thischarge movement within the charge storage layer 3 is primarily based ondrift and diffusion processes which lead to a slow redistribution of thecharges in the charge storage layer 3. The illustration in accordancewith FIG. 1 shows, by way of example, a solid charge distribution curveV, as results shortly after the writing of electrons, for example, atthe local memory locations LB and RB. This distribution V changes,however, on account of drift and diffusion processes, the broadeneddistribution curve V′ illustrated by a broken line being established inthe charge storage layer 3 after a predetermined time has elapsed.However, the charge density stored in the local memory locations LB andRB is reduced as a result. The redistribution of the charges within thecharge storage layer 3 alters the threshold voltage of the semiconductormemory cell, which in turn leads to a loss of information or at least toincreased requirements in the evaluation circuit (not illustrated).

Therefore, the invention is based on the object of providing anonvolatile semiconductor memory cell and an associated fabricationmethod in which improved charge retention properties are obtained.

According to the invention, this object is achieved by means of thefeatures of Patent Claim 1 with regard to the memory cell and by meansof the measures of Patent Claim 5 with regard to the method.

In particular as a result of the use of locally insulated non-conductivecharge storage layers or an electrically non-conductive charge storagelayer which has an interruption in order to form said locally delimitedmemory locations, it is possible firstly to reliably prevent aredistribution on account of the above-described drift and diffusionprocesses in the charge storage layer. Furthermore, it is possible tocompensate for the different accuracies of introduction of holes andelectrons into the storage layer, since the charge storage layer is onlypresent locally in sharply delimited fashion.

Preferably, the first and second insulation layers also have aninterruption or are not connected to one another in a continuous manner,thereby simplifying the fabrication.

In order to realize a semiconductor memory cell having outstandingelectrical properties, a third insulation layer may furthermore beintroduced in the region between the locally delimited memory locationsor in the region of the interruption and may furthermore be coated withan electrically conductive control layer. The electrical properties arethereby improved particularly in the case of large-scale integratedcircuits.

The first insulation layer preferably has a thickness which is greaterthan a material thickness required for direct tunnelling, as a result ofwhich the charge retention properties, in particular, can besignificantly improved.

Further advantageous refinements of the invention are characterized inthe subclaims.

The invention is described in more detail below using an exemplaryembodiment with reference to the drawing.

In the figures:

FIG. 1 shows a simplified sectional view of a semiconductor memory cellin accordance with the prior art;

FIG. 2 shows a simplified sectional view of a nonvolatile semiconductormemory cell according to the invention; and

FIGS. 3A to 3G-II show simplified sectional views for illustratingessential fabrication steps for the nonvolatile semiconductor memorycell according to the invention.

FIG. 2 shows a simplified sectional view of a nonvolatile semiconductormemory cell according to the invention, identical reference symbolsdesignating elements or layers identical or similar to those in FIG. 1,and a repeated description being dispensed with below.

The dual bit EEPROM memory cell described below corresponds to the dualbit memory cell in accordance with document U.S. Pat. No. 6,011,725 inparticular with regard to the method for writing, reading and erasinginformation, for which reason reference is expressly made at thisjuncture to the method disclosed in said document and a repeateddescription is dispensed with.

In accordance with FIG. 2, the nonvolatile semiconductor memory celldesignated as a dual bit EEPROM comprises a substrate 1, in which asource region 7, a drain region 8 and a channel region lying in betweenare formed in a manner comparable to a conventional field-effecttransistor. By way of example, the substrate 1 is composed of a p-dopedsemiconductor material such as e.g. silicon. In the case of the NMOSmemory cell illustrated, the source and drain regions are n⁺-doped, forexample. At the surface of the substrate 1, a first insulation layer 2or a dielectric such as e.g. SiO₂ is in each case situated at least at afirst locally delimited memory location LB (left bit) and a secondlocally delimited memory location RB (right bit). Situated above saidlayer is an electrically non-conductive charge storage layer 3, which isused for the actual storage of the charges introduced. Said electricallynon-conductive charge storage layer 3 again comprises a dielectric suchas e.g. Si₃N₄ or so-called “silicon rich oxide” Si_(2+x)O. At thesurface of said charge storage layer 3, a second insulation layer 4again made of a dielectric such as e.g. SiO₂ is furthermore situated atthe locally delimited memory locations LB and RB. Accordingly, as in thecase of the conventional dual bit semiconductor memory cell, a firstlocal memory location LB (left bit) is formed on the source side and asecond local memory location RB (right bit) is formed on the drain side,which critically influence a current flow in the channel region whenpredetermined voltages are applied, and are thus suitable for storingdata, i.e. two bits.

In contrast to the conventional semiconductor memory cell, however, theelectrically non-conductive charge storage layer 3 is now not connectedtogether in a continuous manner, but rather is interrupted. By virtue ofthis interruption or gap U in the electrically non-conductive chargestorage layer 3, a first locally delimited memory location LB on thesource side and a second locally delimited memory location RB on thedrain side are formed in a completely isolated manner, as a result ofwhich the drift and diffusion processes described in the introductioncannot lead to a loss of data. The charge density in the locallydelimited memory locations LB and RB thus remains unchanged, for whichreason outstanding charge retention properties are obtained.

What is more, however, the formation of the locally delimited memorylocations LB and RB improves the electrical properties of thenonvolatile semiconductor memory cell. As has already been described inthe introduction, the process of writing to the memory locations or theintroduction of charges into the memory locations is effected byinjection of hot charge carriers such as for example in this case by theinjection of electrons which are accelerated in the channel region insuch a way that they can surmount the energy barrier of the firstinsulation layer 2 and pass into the electrically non-conductive chargestorage layer 3. On the other hand, however, these data are erased by acompensation of the introduced charges with correspondingly oppositecharges. By way of example, for erasure purposes, hot holes are injectedinto the locally delimited memory locations LB and RB. However, sincehot holes are usually generated by means of an avalanche effect in thepn diode region at drain or source, the exact location at which theholes ultimately end up in the charge storage layer 3 can be determinedbeforehand only with very great difficulty and generally differs fromthe locations of the electrons. This inaccuracy resulting from theprogramming is compensated for according to the invention by the locallydelimited memory locations LB and RB since, even in the event of awholly inaccurate erasing operation which takes place for example in anoffset manner with respect to the distribution density of the electrons,the latter are left out of consideration and, consequently, do notadversely affect for example the threshold voltages of the memory cell.Only the holes actually introduced into the locally delimited memorylocations LB and RB take effect for a compensation of the electrons.

Consequently, there is an improvement not only in the charge retentionproperties but also in the fundamental electrical properties of thenonvolatile semiconductor memory cell. In particular, the alteration ofthe threshold voltages after repeated writing and erasing operations issignificantly reduced compared with the standard case. Since the chargestorage regions are now restricted to LB and RB, there are now lessstringent requirements made of the accurate superposition of both chargedistributions. A further advantage is thus a simplified development ofthe pn diode and less critical producibility.

The first insulation layer 2 preferably has a thickness which is greaterthan a thickness required for a respective material for directtunnelling. As a result, it is possible to reliably prevent chargelosses on account of direct tunnelling. The same also applies to thesecond insulation layer 4 situated above the charge storage layer 3.

In accordance with FIG. 2, it is not only the electricallynon-conductive charge storage layer 3 that has an interruption U, butalso the first and second insulation layers 2 and 4. As a result,locally highly delimited layer stacks are produced at the locallydelimited memory locations LB and RB, the remaining region in particularat the surface of the channel region being free of said layers. Inaccordance with FIG. 2, a third insulation layer 9, which again has adielectric such as e.g. SiO₂, is thus situated at the surface of thesubstrate 1 and the locally delimited layer stack comprising the layers2, 3 and 4. An electrically conductive control layer 10 is formed at thesurface of said third insulation layer 9, as a result of which the gapor the interruption U between the locally delimited memory locations orthe source and drain regions 7 and 8 is at least partly filled. A fourthinsulation layer 11 may optionally be formed at the surface of theelectrically conductive control layer 10, a post-oxide being used, byway of example.

A method for fabricating the nonvolatile semiconductor memory cellillustrated in FIG. 2 is described below with reference to FIGS. 3A to3G-II, identical reference symbols designating identical orcorresponding layers and a repeated description being dispensed withbelow.

In accordance with FIG. 3A, firstly a first insulation layer 2, anelectrically non-conductive charge storage layer 3, a second insulationlayer 4 and a mask layer 5 are formed on a substrate 1, which has ap-doped silicon semiconductor substrate, by way of example. In order toavoid direct tunnelling effects, the first insulation layer comprises anSiO₂ layer having a thickness of approximately 8 to 10 nm. Directtunnelling occurs for SiO₂ typically in the case of layer thicknesses ofless than 4 to 6 nm. The electrically non-conductive charge storagelayer comprises an Si₃N₄ layer having a thickness of a few nm, but mayalso have so-called “silicon rich oxide”, i.e. Si_(x)O_(y). Silicondioxide having a thickness of 6 to 10 nm, for example, is used for thesecond insulation layer 4, as a result of which a direct tunnelling isalso prevented in this direction. The mask layer 5 is composed, forexample, of a material present in a respective standard process, such ase.g. polysilicon.

In accordance with FIG. 3B, in a subsequent step, the mask layer 5 ispatterned for example by conventional photolithographic or other methodsand an intermediate layer is subsequently formed. Said intermediatelayer comprises a conformally deposited Si₃N₄ layer, which issubsequently used in a conventional etching-back step for fabricatingthe sidewall layers or spacers 6 illustrated in FIG. 3B.

In order to form the layers 2 to 6 described above, it is possible touse all methods that are known for a respective material, such as e.g.CVD (chemical vapour deposition), epitaxial methods and/or thermaloxidation.

In accordance with FIG. 3C, at least the second insulation layer 4 andthe charge storage layer 3 are then removed using the patterned masklayer 5 and the sidewall layers or spacers 6 formed thereon and thesource and drain regions 7 and 8 are subsequently formed in aself-aligning manner in the substrate 1 by means of ion implantation forexample. In this case, the first insulation layer 2 serves as screenmaterial or screen oxide for avoiding so-called “channelling effects”.

In the same way, however, the n⁺-doped source and drain regions can alsobe implemented by direct implantation into the semiconductor substrate1, the first insulation layer 2 also being removed during the patterningusing the patterned mask layer 5 and the sidewall layer 6. It goeswithout saying that so-called pocket implantations can also be inserted.The source and drain regions 7 and 8 also simultaneously realize the bitlines of the nonvolatile semiconductor memory cell or at least theterminal regions for the bit lines.

The fabrication methods for patterning and removing the layers describedabove correspond to conventional patterning and etching methods,anisotropic etching methods preferably being carried out.

In accordance with FIG. 3D, in a subsequent method step, the remainingmask layer 5 and also the second insulation layer 4, the charge storagelayer 3 and the first insulation layer 2 are removed using the sidewalllayers or spacers 6. Anisotropic etching (RIE, reactive ion etching) isonce again preferably carried out in this case, but a degree of thinningof the substrate may result in the source and drain regions 7 and 8.This thinning of the substrate 1 as a result of the etching-back processis generally negligible, however, since it does not cause any negativeeffects on the electrical or other properties of the process or of thememory cell thus fabricated. In this way, an interruption or gap U isobtained for forming locally delimited memory locations LB and RB, whichare arranged essentially in a self-aligning manner on the source sideand on the drain side in each case at the end of the channel. The widthof said locally delimited memory locations can be set very precisely bythe spacer technique used for forming the sidewall layers 6, as a resultof which said memory locations can be defined and arranged exactly evenin a sub-μm or sub-100 nm regime. As a result, in particular theelectrical properties of the memory cell can be greatly improved in thecase of high miniaturization.

In accordance with FIG. 3E, in a subsequent method step, the sidewalllayer or the spacer 6 is removed, conventional selective wet etchingmethods being used, by way of example. In the example of an Si₃N₄ spacer6, hot phosphoric acid can be used for this purpose.

In accordance with FIG. 3F, in a subsequent method step, a thirdinsulation layer 9, which essentially represents a gate oxide layer andis composed of thermally formed SiO₂, for example, is formed over thewhole area. In this way, the layer stacks at the locally delimitedmemory locations also obtain a sufficient sidewall insulation. Thissidewall insulation is preferably again set to a thickness whichprevents direct tunnelling. An electrically conductive control layer 10is subsequently formed, a highly doped polysilicon layer or a metalbeing deposited, by way of example. It is also possible to use otherelectrically conductive layers, such as e.g. siliconized semiconductormaterials.

Furthermore, at this point in time the electrically conductive controllayer 10 is patterned in order to form word lines or word line stripsWL.

FIG. 3F-I and FIG. 3F-II show simplified sectional views of the sectionsI-I′ and II-II′ indicated in FIG. 3F for illustrating the layerstructure after this patterning step.

In accordance with FIG. 3F-I, word lines WL arranged parallel are nowsituated at the surface of the third insulation layer 9, which wasdeposited or formed by thermal oxidation and is again situated on thelayer stack comprising the first insulation layer 2, the charge storagelayer 3 and the second insulation layer 4 on the semiconductor substrate1.

On the other hand, in accordance with FIG. 3F-II, although the patternedword lines WL that run parallel are again situated on the thirdinsulation layer 9, the latter is situated directly on the respectivesource and drain regions 7 and 8 and the substrate 1.

In accordance with FIG. 3G, in a further method step, the thirdinsulation layer 9, the second insulation layer 4, the charge storagelayer 3 and the first insulation layer 2 are selectively removed usingthe patterned control layer 10 or the word lines WL, as a result ofwhich the locally delimited memory locations that were previously formedin strip form are now delimited in this direction as well. Locallydelimited islands are thus produced for the memory locations LB and RB.In particular in the case of a matrix-type arrangement of the memorycells, a complete insulation on adjacent memory locations is thusproduced as well. By way of example, an anisotropic etching method isagain used in this case, a fourth insulation layer 11 finally beingformed in particular for lateral insulation in this direction as well.This fourth insulation layer 11, designated as post-oxide (POX), againpreferably has a layer thickness which prevents a direct tunnelling.

The corresponding sectional views I-I′ and II-II′ of FIG. 3G are againillustrated in FIG. 3G-I and FIG. 3G-II. Consequently, locally delimitedmemory locations LB and RB are obtained in this way, which can bedefined and arranged very exactly in a simple manner in the form ofislands by means of the respective method steps, as a result of which itis possible to significantly influence a drift and diffusion behaviourof introduced charges. In particular, the introduced charge carriers cannow no longer migrate from one end of the channel to the other end ofthe channel, thereby preventing an unintentional alteration of thethreshold voltages in the memory cell. What is more, an improvedprogramming behaviour is obtained since a recombination (compensation)of positive and negative charges takes place significantly faster inthis highly delimited space.

In particular when using so-called “silicon rich oxide” (SRO), it isfurthermore possible to set the mobility of the charge carriers in thecharge storage layer 3 by setting the Si proportion, as a result ofwhich a lateral conductivity can also be set in a defined manner in thelocally delimited memory locations. When Si₃N₄ is used, such setting ofthe mobility of the charge carriers in the charge storage layer 3 iseffected directly by means of the deposition process chosen.

Furthermore, on account of the self-aligning processes, this memory cellis also suitable for very fine structures, it imposing only minorrequirements on an evaluation circuit (not illustrated).

The invention has been described above on the basis of siliconsemiconductor materials. However, it is not restricted thereto and alsoencompasses alternative semiconductor materials in the same way. Othercharge-storing or insulating layers and alternative dopings can also beused in the same way.

1. Method for fabricating a nonvolatile semiconductor memory cell, themethod comprising the following steps: a) formation of a firstinsulation layer (2), an electrically non-conductive charge storagelayer (3), a second insulation layer (4) and a mask layer (5) on asubstrate (1); b) patterning of the mask layer (5); c) formation ofsidewall layers (6) at the patterned mask layer (5); d) removal of atleast a first portion of the second insulation layer (4) and a firstportion of the charge storage layer (3) using the patterned mask layer(5) and the sidewall layer (6); e) formation of source and drain regions(7, 8) in the substrate (1); f) removal of the mask layer (5); g)removal of a second portion of the second insulation layer (4), a secondportion of the charge storage layer (3) and a first portion of the firstinsulation layer (2) using the sidewall layers (6); h) removal of thesidewall layers (6); i) formation of a third insulation layer (9); j)formation of an electrically conductive control layer (10); k)patterning of the control layer (10) in order to form word lines (WL);and l) removal of the third insulation layer (9), a third portion of thesecond insulation layer (4), a third portion of the charge storage layer(3) and a second portion of the first insulation layer (2) using thepatterned control layer (10) in order to form locally delimited memorylocations (LB, RB).
 2. The method as claimed in Patent claim 1,characterized by the following step m) formation of a fourth insulationlayer (11).
 3. Method according to Patent claim 1, characterized in thatan anisotropic etching is carried out in step d), f), g) and/or l). 4.Method according to Patent claim 1, characterized in that a wet etchingis carried out in step h).
 5. Method according to Patent claim 1,characterized in that, in step e), an ion implantation using the firstinsulation layer (2) as screen material is used and the first insulationlayer (2) is 5 subsequently removed (10).
 6. Method according to Patentclaim 1, characterized in that, in step d), the first insulation layer(2) is furthermore removed; and in step e), an ion implantation iscarried out directly into the substrate (1).
 7. Method according toPatent claim 1, characterized in that a thickness of the firstinsulation layer (2) is greater than a material thickness for directtunnelling.
 8. Method according to Patent claim 1, characterized in thatthe first, second, third and/or fourth insulation layer (2,4,9,11)comprises SiO₂.
 9. Method according to Patent claim 1, characterized inthat the electrically non-conductive charge storage layer (3) comprisesSi_(x)O_(y) or Si₃N₄.
 10. Method according to Patent claim 1,characterized in that the control layer (10) and/or the mask layer (5)comprises doped polysilicon, a metal and/or siliconized semiconductormaterial.
 11. Method according to Patent claim 1, characterized in thatthe substrate (1) comprises Si.